C8051F50x-F51x
SFR Definition 19.2. OSCICN: Internal Oscillator Control
Bit
7
6
5
4
3
2
1
0
IOSCEN[1:0]
R/W R/W
SUSPEND
IFRDY
Reserved
IFCN[2:0]
Name
Type
Reset
R/W
0
R
1
R
0
R/W
0
1
1
0
0
SFR Address = 0xA1; SFR Page = 0x0F;
Bit Name
Function
7:6 IOSCEN[1:0] Internal Oscillator Enable Bits.
00: Oscillator Disabled.
01: Reserved.
10: Reserved.
11: Oscillator enabled in normal mode and disabled in suspend mode.
5
4
SUSPEND Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The inter-
nal oscillator resumes operation when one of the SUSPEND mode awakening
events occurs.
IFRDY
Internal Oscillator Frequency Ready Flag.
0: Internal oscillator is not running at programmed frequency.
1: Internal oscillator is running at programmed frequency.
3
Reserved Read = 0b; Must Write = 0b.
2:0
IFCN[2:0] Internal Oscillator Frequency Divider Control Bits.
000: SYSCLK derived from Internal Oscillator divided by 128.
001: SYSCLK derived from Internal Oscillator divided by 64.
010: SYSCLK derived from Internal Oscillator divided by 32.
011: SYSCLK derived from Internal Oscillator divided by 16.
100: SYSCLK derived from Internal Oscillator divided by 8.
101: SYSCLK derived from Internal Oscillator divided by 4.
110: SYSCLK derived from Internal Oscillator divided by 2.
111: SYSCLK derived from Internal Oscillator divided by 1.
168
Rev. 1.1
SILICON [ SILICON ]
