C8051F50x-F51x
SFR Definition 19.5. CLKMUL: Clock Multiplier
Bit
7
6
5
4
3
2
1
0
MULEN
MULINIT MULRDY
MULDIV[2:0]
MULSEL[1:0]
R/W
Name
Type
Reset
R/W
0
R/W
0
R
0
R/W
0
0
0
0
0
SFR Address = 0x97; SFR Page = 0x0F;
Bit
Name
Function
7
MULEN
Clock Multiplier Enable.
0: Clock Multiplier disabled.
1: Clock Multiplier enabled.
6
5
MULINIT
MULRDY
Clock Multiplier Initialize.
This bit is 0 when the Clock Multiplier is enabled. Once enabled, writing a 1 to this
bit will initialize the Clock Multiplier. The MULRDY bit reads 1 when the Clock Mul-
tiplier is stabilized.
Clock Multiplier Ready.
0: Clock Multiplier is not ready.
1: Clock Multiplier is ready (PLL is locked).
4:2 MULDIV[2:0] Clock Multiplier Output Scaling Factor.
000: Clock Multiplier Output scaled by a factor of 1.
001: Clock Multiplier Output scaled by a factor of 1.
010: Clock Multiplier Output scaled by a factor of 1.
011: Clock Multiplier Output scaled by a factor of 2/3*.
100: Clock Multiplier Output scaled by a factor of 2/4 (1/2).
101: Clock Multiplier Output scaled by a factor of 2/5*.
110: Clock Multiplier Output scaled by a factor of 2/6 (1/3).
111: Clock Multiplier Output scaled by a factor of 2/7*.
*Note: The Clock Multiplier output duty cycle is not 50% for these settings.
1:0 MULSEL[1:0] Clock Multiplier Input Select.
These bits select the clock supplied to the Clock Multiplier
Clock Multiplier Output
MULSEL[1:0]
Selected Input Clock
for MULDIV[2:0] = 000b
Internal Oscillator x 2
00
01
10
11
Internal Oscillator
External Oscillator
Internal Oscillator
External Oscillator
External Oscillator x 2
Internal Oscillator x 4
External Oscillator x 4
Notes:The maximum system clock is 50 MHz, and so the Clock Multiplier output should be scaled accordingly.
If Internal Oscillator x 2 or External Oscillator x 2 is selected using the MULSEL bits, MULDIV[2:0] is ignored.
Rev. 1.1
171
SILICON [ SILICON ]
