C8051F50x-F51x
SFR Definition 19.1. CLKSEL: Clock Select
Bit
7
6
5
4
3
2
1
0
CLKSL[1:0]
R/W
Name
Type
Reset
R
0
R
0
R
0
R
0
R
0
R
0
0
0
SFR Address = 0x8F; SFR Page = 0x0F;
Bit
Name
Function
7:2
Unused
Read = 000000b; Write = Don’t Care
1:0 CLKSL[1:0] System Clock Source Select Bits.
00: SYSCLK derived from the Internal Oscillator and scaled per the IFCN bits in reg-
ister OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Clock Multiplier.
11: reserved.
Important Note: If the selected system clock is greater than 25 MHz, please be aware of the following:
Flash Scale Timing must be configured for the faster system clock. See SFR Definition 15.3 for more
details.
VDD and VDDA voltage must be 2 V or higher.
It is recommended to enable the VDD monitor as a reset source and configure it for the high threshold.
See SFR Definition 17.1 for details on configuring the VDD monitor. If the VDD monitor is configured to
the high threshold, the VDD and VDDA voltage must be greater than the VDD monitor high threshold.
See Table 5.4 for VDD monitor threshold specifications.
166
Rev. 1.1
SILICON [ SILICON ]
