C8051F50x-F51x
Table 18.3. AC Parameters for External Memory Interface
Parameter
Description
Min*
Max*
Units
Address/Control Setup Time
0
3 x TSYSCLK
ns
T
ACS
Address/Control Pulse Width
Address/Control Hold Time
Address Latch Enable High Time
Address Latch Enable Low Time
Write Data Setup Time
1 x TSYSCLK
16 x TSYSCLK
3 x TSYSCLK
4 x TSYSCLK
4 x TSYSCLK
19 x TSYSCLK
3 x TSYSCLK
ns
ns
ns
ns
ns
ns
ns
ns
T
ACW
0
T
ACH
1 x TSYSCLK
T
ALEH
1 x TSYSCLK
T
ALEL
1 x TSYSCLK
T
WDS
Write Data Hold Time
0
20
0
T
WDH
Read Data Setup Time
T
T
RDS
Read Data Hold Time
RDH
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
164
Rev. 1.1
SILICON [ SILICON ]
