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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
18.5. Memory Mode Selection  
The external data memory space can be configured in one of four modes, shown in Figure 18.3, based on  
the EMIF Mode bits in the EMI0CF register (SFR Definition 18.2). These modes are summarized below.  
More information about the different modes can be found in Section “18.6. Timing” on page 156.  
EMI0CF[3:2] = 00  
EMI0CF[3:2] = 01  
EMI0CF[3:2] = 10  
EMI0CF[3:2] = 11  
0xFFFF  
0xFFFF  
0xFFFF  
0xFFFF  
On-Chip XRAM  
On-Chip XRAM  
On-Chip XRAM  
On-Chip XRAM  
On-Chip XRAM  
On-Chip XRAM  
Off-Chip  
Memory  
(No Bank Select)  
Off-Chip  
Memory  
(Bank Select)  
Off-Chip  
Memory  
On-Chip XRAM  
On-Chip XRAM  
0x0000  
0x0000  
0x0000  
0x0000  
Figure 18.3. EMIF Operating Modes  
18.5.1. Internal XRAM Only  
When bits EMI0CF[3:2] are set to 00, all MOVX instructions will target the internal XRAM space on the  
device. Memory accesses to addresses beyond the populated space will wrap on 4 kB boundaries. As an  
example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space.  
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address  
and R0 or R1 to determine the low-byte of the effective address.  
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.  
18.5.2. Split Mode without Bank Select  
When bit EMI0CF.[3:2] are set to 01, the XRAM memory map is split into two areas, on-chip space and off-  
chip space.  
Effective addresses below the internal XRAM size boundary will access on-chip XRAM space.  
Effective addresses above the internal XRAM size boundary will access off-chip space.  
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-  
chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the  
upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate  
the upper address bits at will by setting the Port state directly via the port latches. This behavior is in  
contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0]  
are driven, determined by R0 or R1.  
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip  
or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven  
during the off-chip transaction.  
Rev. 1.1  
155