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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
SFR Definition 18.3. EMI0TC: External Memory Timing Control  
Bit  
7
6
5
4
3
2
1
0
EAS[1:0]  
R/W  
EWR[3:0]  
R/W  
EAH[1:0]  
R/W  
Name  
Type  
Reset  
1
1
1
1
1
1
1
1
SFR Address = 0xAA; SFR Page = 0x0F  
Bit  
Name  
Function  
7:6  
EAS[1:0] EMIF Address Setup Time Bits.  
00: Address setup time = 0 SYSCLK cycles.  
01: Address setup time = 1 SYSCLK cycle.  
10: Address setup time = 2 SYSCLK cycles.  
11: Address setup time = 3 SYSCLK cycles.  
5:2 EWR[3:0] EMIF WR and RD Pulse-Width Control Bits.  
0000: WR and RD pulse width = 1 SYSCLK cycle.  
0001: WR and RD pulse width = 2 SYSCLK cycles.  
0010: WR and RD pulse width = 3 SYSCLK cycles.  
0011: WR and RD pulse width = 4 SYSCLK cycles.  
0100: WR and RD pulse width = 5 SYSCLK cycles.  
0101: WR and RD pulse width = 6 SYSCLK cycles.  
0110: WR and RD pulse width = 7 SYSCLK cycles.  
0111: WR and RD pulse width = 8 SYSCLK cycles.  
1000: WR and RD pulse width = 9 SYSCLK cycles.  
1001: WR and RD pulse width = 10 SYSCLK cycles.  
1010: WR and RD pulse width = 11 SYSCLK cycles.  
1011: WR and RD pulse width = 12 SYSCLK cycles.  
1100: WR and RD pulse width = 13 SYSCLK cycles.  
1101: WR and RD pulse width = 14 SYSCLK cycles.  
1110: WR and RD pulse width = 15 SYSCLK cycles.  
1111: WR and RD pulse width = 16 SYSCLK cycles.  
1:0  
EAH[1:0] EMIF Address Hold Time Bits.  
00: Address hold time = 0 SYSCLK cycles.  
01: Address hold time = 1 SYSCLK cycle.  
10: Address hold time = 2 SYSCLK cycles.  
11: Address hold time = 3 SYSCLK cycles.  
Rev. 1.1  
157