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C8051F339 参数 Datasheet PDF下载

C8051F339图片预览
型号: C8051F339
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
3. Pin Definitions  
Table 3.1. Pin Definitions for the C8051F336/7/8/9  
Pin  
‘F336/7  
Pin  
‘F338/9  
Name  
Type  
Description  
V
3
2
4
3
Power Supply Voltage.  
Ground.  
DD  
GND  
Note: This ground connection is required. The center pad may  
optionally be connected to ground also.  
RST/  
4
5
5
D I/O Device Reset. Open-drain output of internal POR or V  
DD  
monitor. An external source can initiate a system reset by  
driving this pin low for at least 10 µs.  
C2CK  
P2.0/  
D I/O Clock signal for the C2 Debug Interface.  
D I/O Port 2.0.  
C2D  
D I/O Bi-directional data signal for the C2 Debug Interface.  
D I/O Port 2.4.  
P2.4/  
6
2
C2D  
D I/O Bi-directional data signal for the C2 Debug Interface.  
P0.0/  
1
D I/O or Port 0.0.  
A In  
VREF  
P0.1  
A In  
External VREF input.  
20  
19  
1
D I/O or Port 0.1.  
A In  
IDA0  
P0.2/  
AOut IDA0 Output.  
24  
D I/O or Port 0.2.  
A In  
XTAL1  
P0.3/  
A In  
External Clock Input. This pin is the external oscillator  
return for a crystal or resonator.  
18  
17  
23  
22  
D I/O or Port 0.3.  
A In  
XTAL2  
P0.4  
A I/O or External Clock Output. For an external crystal or resonator,  
D In  
this pin is the excitation driver. This pin is the external clock  
input for CMOS, capacitor, or RC oscillator configurations.  
D I/O or Port 0.4.  
A In  
28  
Rev. 0.2