C8051F336/7/8/9
1.8. Comparator
C8051F336/7/8/9 devices include an on-chip voltage comparator that is enabled/disabled and configured
via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two compar-
ator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous)
output. Comparator response time is programmable, allowing the user to select between high-speed and
low-power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-
rupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.9 shows the Comparator0 block diagram.
CPT0MX
CPT0CN
P0.0
P0.2
VDD
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P2.0
P2.2
CP0 +
CP0 -
+
-
CP0
SET
CLR
SET
CLR
D
Q
Q
D
Q
Q
P0.1
P0.3
P0.5
P0.7
P1.1
P1.3
P1.5
P1.7
P2.1
P2.3
Crossbar
(SYNCHRONIZER)
CP0A
GND
Reset
CPT0MD
Decision
Tree
0
1
CP0
Interrupt
CP0EN
EA
CP0RIF
CP0FIF
0
0
1
1
0
1
Figure 1.9. Comparator0 Block Diagram
Rev. 0.2
25
SILICON [ SILICON ]
