C8051F336/7/8/9
1.7. 10-Bit Analog to Digital Converter
The C8051F336/8 devices include an on-chip 10-bit SAR ADC with a differential input multiplexer. With a
maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and DNL of ±1 LSB. The
ADC system includes a configurable analog multiplexer that selects both positive and negative ADC
inputs. Up to twenty port I/O pins are available as an ADC inputs; additionally, the on-chip Temperature
Sensor output and the power supply voltage (V ) are available as ADC inputs. User firmware may shut
DD
down the ADC to save power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is
either within or outside of a specified range. The ADC can monitor a key voltage continuously in back-
ground mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
P0.0
Configuration, Control, and Data Registers
AMUX
000
001
010
011
100
101
AD0BUSY (W)
P2.3
Start
Conversion
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
Temp
Sensor
VDD
P0.0
10-Bit
SAR
(+)
(-)
ADC Data
Registers
16
ADC
AMUX
P2.3
Window
Compare
Interrupt
Window Compare
Logic
VREF
GND
End of
Conversion
Interrupt
Figure 1.8. 10-Bit ADC Block Diagram
24
Rev. 0.2
SILICON [ SILICON ]
