C8051F336/7/8/9
Table 15.1. Interrupt Summary
Interrupt Source
Interrupt Priority
Pending Flag
Enable
Flag
Priority
Control
Vector
Order
Always
Enabled
Always
Highest
Reset
0x0000
Top
None
N/A N/A
External Interrupt 0
(/INT0)
Timer 0 Overflow
External Interrupt 1
(/INT1)
0x0003
0x000B
0x0013
0x001B
0x0023
0
1
2
3
4
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
EX0 (IE.0) PX0 (IP.0)
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2) PX1 (IP.2)
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4) PS0 (IP.4)
Timer 1 Overflow
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
UART0
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Timer 2 Overflow
0x002B
0x0033
5
6
Y
Y
Y
N
N
N
ET2 (IE.5) PT2 (IP.5)
ESPI0
(IE.6)
PSPI0
(IP.6)
SPI0
ESMB0
(EIE1.0)
EMAT
PSMB0
(EIP1.0)
PMAT
SMB0
0x003B
0x0043
0x004B
0x0053
7
SI (SMB0CN.0)
None
Port Match
8
N/A N/A
(EIE1.1)
(EIP1.1)
ADC0 Window
Compare
ADC0 Conversion
Complete
AD0WINT
(ADC0CN.3)
EWADC0 PWADC0
9
Y
Y
N
N
(EIE1.2)
EADC0
(EIE1.3)
(EIP1.2)
PADC0
(EIP1.3)
10
AD0INT (ADC0CN.5)
CF (PCA0CN.7)
CCFn (PCA0CN.n)
COVF (PCA0PWM.6)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
N/A
Programmable
Counter Array
EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
0x005B
11
Y
N
ECP0
(EIE1.5)
N/A N/A N/A
ET3
PCP0
(EIP1.5)
N/A
PT3
(EIP1.7)
Comparator0
RESERVED
0x0063
0x006B
0x0073
12
13
14
N
N
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
Timer 3 Overflow
N
N
(EIE1.7)
15.2. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in this section.
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Rev. 0.2
91
SILICON [ SILICON ]
