C8051F336/7/8/9
Table 14.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
REF0CN
RSTSRC
SBUF0
Address
0xD1
0xEF
0x99
0x98
0xE7
0xD7
0xC1
0xC0
0xC2
0x81
0xA1
0xA2
0xF8
0xA3
0x88
0x8C
0x8D
0x8A
0x8B
0x89
0xC8
0xCD
0xCC
0xCB
0xCA
0x91
0x95
0x94
0x93
0x92
0xFF
0xE1
0xE2
Description
Voltage Reference Control
Page
64
Reset Source Configuration/Status
UART0 Data Buffer
115
172
171
156
156
151
153
157
79
SCON0
SMB0ADM
SMB0ADR
SMB0CF
SMB0CN
SMB0DAT
SP
UART0 Control
SMBus Slave Address Mask
SMBus Slave Address
SMBus Configuration
SMBus Control
SMBus Data
Stack Pointer
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
TCON
SPI Configuration
181
183
182
183
193
196
196
195
195
194
200
202
201
201
201
206
208
207
207
207
113
134
135
SPI Clock Rate Control
SPI Control
SPI Data
Timer/Counter Control
Timer/Counter 0 High
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Control
Timer/Counter 2 High
Timer/Counter 2 Low
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
Timer/Counter 3Control
Timer/Counter 3 High
Timer/Counter 3Low
Timer/Counter 3 Reload High
Timer/Counter 3 Reload Low
TH0
TH1
TL0
TL1
TMOD
TMR2CN
TMR2H
TMR2L
TMR2RLH
TMR2RLL
TMR3CN
TMR3H
TMR3L
TMR3RLH
TMR3RLL
VDM0CN
XBR0
V
Monitor Control
DD
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
XBR1
88
Rev. 0.2
SILICON [ SILICON ]
