C8051F336/7/8/9
SFR Definition 15.3. EIE1: Extended Interrupt Enable 1
Bit
7
6
Reserved
R/W
5
ECP0
R/W
0
4
EPCA0
R/W
0
3
EADC0
R/W
0
2
EWADC0
R/W
1
EMAT
R/W
0
0
ESMB0
R/W
0
Name
Type
Reset
ET3
R/W
0
0
0
SFR Address = 0xE6
Bit
Name
Function
7
ET3
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
Reserved Reserved. Must Write 0.
ECP0 Enable Comparator0 (CP0) Interrupt.
6
5
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
4
3
2
1
0
EPCA0 Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EADC0 Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
EWADC0 Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
EMAT
Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
ESMB0 Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
94
Rev. 0.2
SILICON [ SILICON ]
