C8051F39x/37x
16. Prefetch Engine
The C8051F39x/37x family of devices incorporate a 2-byte prefetch engine. Because the access time of
the Flash memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is nec-
essary for full-speed code execution. Instructions are read from Flash memory two bytes at a time by the
prefetch engine and given to the CIP-51 processor core to execute. When running linear code (code with-
out any jumps or branches), the prefetch engine allows instructions to be executed at full speed. When a
code branch occurs, the processor may be stalled for up to two clock cycles while the next set of code
bytes is retrieved from Flash memory.
Note: The prefetch engine should be disabled when the device is in suspend mode to save power.
SFR Definition 16.1. PFE0CN: Prefetch Engine Control
Bit
7
6
5
4
3
2
1
0
PFEN
Name
Type
Reset
R
0
R
0
R/W
1
R
0
R
0
R
0
R
0
R
0
SFR Address = 0xB5; SFR Page = All Pages
Bit
Name
Function
7:6
5
Unused
PFEN
Unused. Read = 00b, Write = don’t care.
Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
4:0
Unused
Unused. Read = 00000b. Write = don’t care.
90
Preliminary Rev. 0.71
SILICON [ SILICON ]
