C8051F39x/37x
SFR Definition 15.6. PSW: Program Status Word
Bit
7
6
5
4
3
2
1
0
CY
AC
F0
RS[1:0]
R/W
OV
F1
PARITY
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
0
0
SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
CY
Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry
(addition) or a borrow (subtraction). It is cleared to logic 0 by all
other arithmetic operations.
6
AC
Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry
into (addition) or a borrow from (subtraction) the high order nibble.
It is cleared to logic 0 by all other arithmetic operations.
5
F0
User Flag 0.
This is a bit-addressable, general purpose flag for use under soft-
ware control.
4:3
RS[1:0]
Register Bank Select.
These bits select which register bank is used during register
accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2
OV
Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change
overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and
DIV instructions in all other cases.
1
0
F1
User Flag 1.
This is a bit-addressable, general purpose flag for use under soft-
ware control.
PARITY
Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumula-
tor is odd and cleared if the sum is even.
Preliminary Rev. 0.71
89
SILICON [ SILICON ]
