C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 18.1. SMB0CF: SMBus Clock/Configuration
SFR Page:
all pages
SFR Address: 0xC1
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Reset Value
ENSMB
INH
BUSY EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCS0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit 7:
ENSMB: SMBus Enable.
This bit enables/disables the SMBus interface. When enabled, the interface constantly mon-
itors the SDA and SCL pins.
0: SMBus interface disabled.
1: SMBus interface enabled.
Bit 6:
INH: SMBus Slave Inhibit.
When this bit is set to logic ‘1’, the SMBus does not generate an interrupt when slave events
occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are
not affected.
0: SMBus Slave Mode enabled.
1: SMBus Slave Mode inhibited.
Bit 5:
Bit 4:
BUSY: SMBus Busy Indicator.
This bit is set to logic ‘1’ by hardware when a transfer is in progress. It is cleared to logic ‘0’
when a STOP or free-timeout is sensed.
EXTHOLD: SMBus Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times according to:
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
Bit 3:
SMBTOE: SMBus SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic ‘1’, the SMBus forces Timer 3 to
reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is con-
figured to Split Mode, only the High Byte of the timer is held in reload while SCL is high.
Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt
service routine should reset SMBus communication.
SMBFTE: SMBus Free Timeout Detection Enable.
Bit 2:
When this bit is set to logic ‘1’, the bus will be considered free if SCL and SDA remain high
for more than 10 SMBus clock source periods.
Bits 1–0: SMBCS1–SMBCS0: SMBus Clock Source Selection.
These two bits select the SMBus clock source, which is used to generate the SMBus bit
rate. The selected device should be configured according to Equation 18.1.
SMBCS1 SMBCS0
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
0
0
1
1
0
1
0
1
208
Rev. 1.0
SILICON [ SILICON ]
