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C8051F363 参数 Datasheet PDF下载

C8051F363图片预览
型号: C8051F363
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
SFR Definition 17.4. P0MDIN: Port0 Input Mode  
SFR Page:  
F
SFR Address: 0xF1  
R/W  
R/W  
Bit6  
R/W  
Bit5  
R/W  
Bit4  
R/W  
Bit3  
R/W  
Bit2  
R/W  
Bit1  
R/W  
Bit0  
Reset Value  
11111111  
Bit7  
Bits 7–0: Analog Input Configuration Bits for P0.7-P0.0 (respectively).  
Port pins configured as analog inputs have their weak pullup, digital driver, and digital  
receiver disabled.  
0: Corresponding P0.n pin is configured as an analog input.  
1: Corresponding P0.n pin is not configured as an analog input.  
SFR Definition 17.5. P0MDOUT: Port0 Output Mode  
SFR Page:  
F
SFR Address: 0xA4  
R/W  
R/W  
R/W  
Bit5  
R/W  
Bit4  
R/W  
Bit3  
R/W  
Bit2  
R/W  
Bit1  
R/W  
Bit0  
Reset Value  
00000000  
Bit7  
Bit6  
Bits 7–0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in regis-  
ter P0MDIN is logic ‘0’.  
0: Corresponding P0.n Output is open-drain.  
1: Corresponding P0.n Output is push-pull.  
Note:  
When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of  
P0MDOUT.  
Rev. 1.0  
191  
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