C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 17.1. XBR0: Port I/O Crossbar Register 0
SFR Page:
F
SFR Address: 0xE1
R/W
R/W
R/W
CP0AE
Bit5
R/W
CP0E
Bit4
R/W
R/W
R/W
SPI0E
Bit1
R/W
Reset Value
CP1AE
Bit7
CP1E
Bit6
SYSCKE SMB0E
URT0E 00000000
Bit0
Bit3
Bit2
Bit 7:
CP1AE: Comparator1 Asynchronous Output Enable
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
CP1E: Comparator1 Output Enable
0: CP1 unavailable at Port pin.
Bit 6:
Bit 5:
Bit 4:
Bit 3:
1: CP1 routed to Port pin.
CP0AE: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK (divided by 1, 2, 4, or 8) routed to Port pin. The divide factor is determined by
the CLKDIV1–0 bits in register CLKSEL (See Section Section “16. Oscillators” on
page 169).
Bit 2:
Bit 1:
Bit 0:
SMB0E: SMBus I/O Enable
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI0E: SPI I/O Enable
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins.
URT0E: UART I/O Output Enable
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.1 and P0.2 (C8051F360/3) or P0.4 and P0.5
(C8051F361/2/4/5/6/7/8/9).
188
Rev. 1.0
SILICON [ SILICON ]
