C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 17.11. P1MDOUT: Port1 Output Mode
SFR Page:
F
SFR Address: 0xA5
R/W
R/W
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
Bit7
Bit6
Bits 7–0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis-
ter P1MDIN is logic ‘0’.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
SFR Definition 17.12. P1SKIP: Port1 Skip
SFR Page:
F
SFR Address: 0xD5
R/W
R/W
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
Bit7
Bit6
Bits 7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (V
input, external oscil-
REF
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
SFR Definition 17.13. P1MAT: Port1 Match
SFR Page:
0
SFR Address: 0xE1
R/W
R/W
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
11111111
Bit7
Bit6
Bits 7–0: P1MAT[7:0]: Port1 Match Value.
These bits control the value that unmasked P0 Port pins are compared against. A Port
Match event is generated if (P1 & P1MASK) does not equal (P1MAT & P1MASK).
194
Rev. 1.0
SILICON [ SILICON ]
