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C8051F363 参数 Datasheet PDF下载

C8051F363图片预览
型号: C8051F363
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
17.2. Port I/O Initialization  
Port I/O initialization consists of the following steps:  
Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode  
register (PnMDIN).  
Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output  
Mode register (PnMDOUT).  
Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).  
Step 4. Assign Port pins to desired peripherals using the XBRn registers.  
Step 5. Enable the Crossbar (XBARE = ‘1’).  
All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or  
ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its  
weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise  
on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however, this  
practice is not recommended.  
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by  
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates  
a digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset. See SFR Defini-  
tion 17.4 for the PnMDIN register details.  
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-  
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is  
required even for the digital resources selected in the XBRn registers, and is not automatic. The only  
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the  
PnMDOUT settings. When the WEAKPUD bit in XBR1 is ‘0’, a weak pullup is enabled for all Port I/O con-  
figured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is  
turned off on an output that is driving a ‘0’ and for pins configured for analog input mode to avoid unneces-  
sary power dissipation.  
Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions  
required by the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is  
enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register  
settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode  
Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the  
Port I/O pin-assignments based on the XBRn Register settings.  
The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers  
are disabled while the Crossbar is disabled.  
Rev. 1.0  
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