C8051F360/1/2/3/4/5/6/7/8/9
P0
P1
P2
P3
P3.5-P3.7
available
on 48-pin
only
SF Signals
(32- and 28-
pin)
P3.1-P3.4
available on
32/48-pin only
SF Signals
(48-pin)
PIN I/O
TX0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
(32-pin and 28-pin packages)
(48-pin package)
RX0
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
(*4-Wire SPI Only)
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
P3SKIP[0:7]
Figure 17.4. Crossbar Priority Decoder with Port Pins Skipped
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.1
(C8051F360/3) or P0.4 (C8051F361/2/4/5/6/7/8/9); UART RX0 is always assigned to P0.2 (C8051F360/3)
or P0.5 (C8051F361/2/4/5/6/7/8/9). Standard Port I/Os appear contiguously starting at P0.0 after prioritized
functions and skipped pins are assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
186
Rev. 1.0
SILICON [ SILICON ]
