C8051F360/1/2/3/4/5/6/7/8/9
Table 16.3. PLL Frequency Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Input Frequency
(Divided Reference Frequency)
Conditions
Min
5
Typ
Max
30
Units
MHz
MHz
25
100*
PLL Output Frequency
*Note: The maximum operating frequency of the C8051F366/7/8/9 is 50 MHz.
Table 16.4. PLL Lock Timing Characteristics
–40 to +85 °C unless otherwise specified
Input
Frequency
Multiplier
(Pll0mul)
Pll0flt
Setting
0x0F
0x0F
0x1F
0x1F
0x2F
0x2F
0x3F
0x3F
0x01
0x01
0x11
Output
Frequency
100 MHz
65 MHz
80 MHz
45 MHz
60 MHz
30 MHz
50 MHz
25 MHz
100 MHz
50 MHz
75 MHz
50 MHz
50 MHz
25 MHz
50 MHz
25 MHz
Min
Typ
Max
Units
20
13
16
9
12
6
10
5
4
2
3
2
2
202
115
241
116
258
112
263
113
42
33
48
17
42
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
5 MHz
0x11
25 MHz
0x21
0x21
0x31
0x31
1
2
1
33
60
25
182
Rev. 1.0
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