C8051F360/1/2/3/4/5/6/7/8/9
16.1.1. Internal Oscillator Suspend Mode
When software writes a logic ‘1’ to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
•
•
•
•
•
Port 0 Match Event.
Port 1 Match Event.
Port 2 Match Event.
Comparator 0 enabled and output is logic ‘0’.
Comparator 1 enabled and output is logic ‘0’.
When one of the internal oscillator awakening events occur, the internal oscillator, CIP-51, and affected
peripherals resume normal operation, regardless of whether the event also causes an interrupt. The CPU
resumes execution at the instruction following the write to SUSPEND.
Note: Before entering SUSPEND mode, SYSCLK should be switched to run off of the internal oscillator
and not the PLL. When the CPU wakes due to the awakening event, the PLL must be reinitialized before
switching back to it as the SYSCLK source.
SFR Definition 16.1. OSCICL: Internal Oscillator Calibration.
SFR Page:
F
SFR Address: 0xBF
R/W
Bit7
R/W
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
Variable
Bit6
Bits 7–0: OSCICL: Internal Oscillator Calibration Register.
This register calibrates the internal oscillator period. The reset value for OSCICL defines the
internal oscillator base frequency. The reset value is factory calibrated to generate an inter-
nal oscillator frequency of 24.5 MHz.
170
Rev. 1.0
SILICON [ SILICON ]
