C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 16.4. CLKSEL: System Clock Selection
SFR Page:
F
SFR Address: 0x8F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved CLKDIV1 CLKDIV0 Reserved CLKSL2 CLKSL1 CLKSL0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–6: RESERVED. Read = 00b. Must Write 00b.
Bits 5–4: CLKDIV1-0: Output SYSCLK Divide Factor.
These bits can be used to pre-divide SYSCLK before it is output to a port pin through the
crossbar.
00: Output will be SYSCLK.
01: Output will be SYSCLK/2.
10: Output will be SYSCLK/4.
11: Output will be SYSCLK/8.
See Section “17. Port Input/Output” on page 183 for more details about routing this output to
a port pin.
Bit 3:
RESERVED. Read = 0b. Must Write 0b.
Bits 2–0: CLKSL2–0: System Clock Source Select Bits.
000: SYSCLK derived from the high-frequency Internal Oscillator, and scaled as per the
IFCN bits in OSCICN.
001: SYSCLK derived from the External Oscillator circuit.
010: SYSCLK derived from the low-frequency Internal Oscillator, and scaled as per the
OSCLD bits in OSCLCN.
011: RESERVED.
100: SYSCLK derived from the PLL.
101-11x: RESERVED.
174
Rev. 1.0
SILICON [ SILICON ]
