C8051F360/1/2/3/4/5/6/7/8/9
Table 15.2. AC Parameters for External Memory Interface
Parameter
Description
Min*
Max*
3 x T
Units
T
Address/Control Setup Time
0
ns
ACS
SYSCLK
T
Address/Control Pulse Width
Address/Control Hold Time
Address Latch Enable High Time
Address Latch Enable Low Time
Write Data Setup Time
1 x T
16 x T
ns
ns
ns
ns
ns
ns
ns
ns
ACW
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
T
0
3 x T
4 x T
4 x T
ACH
T
1 x T
1 x T
1 x T
ALEH
SYSCLK
SYSCLK
T
ALEL
T
19 x T
WDS
WDH
SYSCLK
SYSCLK
3 x T
SYSCLK
T
Write Data Hold Time
0
T
T
Read Data Setup Time
20
0
RDS
Read Data Hold Time
RDH
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
168
Rev. 1.0
SILICON [ SILICON ]
