C8051F360/1/2/3/4/5/6/7/8/9
Table 10.1. Interrupt Summary (Continued)
Interrupt Priority
Enable
Flag
Priority
Control
Interrupt Source
Pending Flag
Vector
Order
Programmable Counter
Array
CF (PCA0CN.7)
EPCA0
(EIE1.4)
ECP0
(EIE1.5)
ECP1
(EIE1.6)
ET3
(EIE1.7)
N/A
EMAT
(EIE2.1)
PPCA0
(EIP1.4)
PCP0
(EIP1.5)
PCP1
(EIP1.6)
PT3
(EIP1.7)
N/A
PMAT
0x005B
0x0063
0x006B
11
12
13
Y
N
N
N
N
N
N
N
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
N/A
Comparator0
Comparator1
Timer 3 Overflow
RESERVED
Port Match
0x0073
0x007B
0x0083
14
15
16
N/A N/A
N/A N/A
N/A
(EIP2.1)
10.4. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Rev. 1.0
109
SILICON [ SILICON ]
