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C8051F363 参数 Datasheet PDF下载

C8051F363图片预览
型号: C8051F363
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
10.2. Interrupt Priorities  
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-  
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be  
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to  
configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the  
interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed prior-  
ity order is used to arbitrate, given in Table 10.1.  
10.3. Interrupt Latency  
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are  
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is  
5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the  
ISR. Additional clock cycles will be required if a cache miss occurs (see Section 14 for more details). If an  
interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to  
service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other inter-  
rupt is currently being serviced or the new interrupt is of greater priority) is when the CPU is performing an  
RETI instruction followed by a DIV as the next instruction, and a cache miss event also occurs. If the CPU  
is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until  
the current ISR completes, including the RETI and following instruction.  
Table 10.1. Interrupt Summary  
Interrupt Priority  
Enable  
Flag  
Priority  
Control  
Interrupt Source  
Pending Flag  
Vector  
Order  
Always  
Enabled  
Always  
Highest  
Reset  
0x0000  
Top None  
N/A N/A  
External Interrupt 0 (/INT0) 0x0003  
Timer 0 Overflow 0x000B  
External Interrupt 1 (/INT1) 0x0013  
0
1
2
3
IE0 (TCON.1)  
TF0 (TCON.5)  
IE1 (TCON.3)  
TF1 (TCON.7)  
Y
Y
Y
Y
Y
Y
Y
Y
EX0 (IE.0) PX0 (IP.0)  
ET0 (IE.1) PT0 (IP.1)  
EX1 (IE.2) PX1 (IP.2)  
ET1 (IE.3) PT1 (IP.3)  
Timer 1 Overflow  
0x001B  
RI0 (SCON0.0)  
TI0 (SCON0.1)  
UART0  
0x0023  
4
5
Y
Y
N
N
ES0 (IE.4) PS0 (IP.4)  
ET2 (IE.5) PT2 (IP.5)  
TF2H (TMR2CN.7)  
TF2L (TMR2CN.6)  
SPIF (SPI0CN.7)  
WCOL (SPI0CN.6)  
MODF (SPI0CN.5)  
RXOVRN (SPI0CN.4)  
Timer 2 Overflow  
SPI0  
0x002B  
0x0033  
ESPI0  
(IE.6)  
PSPI0  
(IP.6)  
6
Y
N
ESMB0  
(EIE1.0)  
N/A  
PSMB0  
(EIP1.0)  
N/A  
SMB0  
0x003B  
0x0043  
0x004B  
7
8
9
SI (SMB0CN.0)  
Y
N
RESERVED  
ADC0 Window  
Comparator  
N/A  
AD0WINT  
(ADC0CN.5)  
N/A N/A  
EWADC0 PWADC0  
Y
Y
N
N
(EIE1.2)  
EADC0  
(EIE1.3)  
(EIP1.2)  
PADC0  
(EIP1.3)  
ADC0 End of Conversion  
0x0053  
10  
AD0INT (ADC0STA.5)  
108  
Rev. 1.0