BATTERY PROTECTION IC FOR 1-CELL PACK
S-8241 Series
Rev.7.6_00
Test Circuits
Caution Unless otherwise specified, the output voltage levels “H” and “L” at CO pin (VCO) and DO pin (VDO) are
judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to VVM
and the DO pin level with respect to VSS
.
(1) Test Condition 1, Test Circuit 1
(Overcharge detection voltage, Overcharge release voltage, Overdischarge detection voltage, Overdischarge
release voltage)
The overcharge detection voltage (VCU) is defined by the voltage between VDD and VSS at which VCO goes “L” from “H”
when the voltage V1 is gradually increased from the normal condition V1 = 3.5 V and V2 = 0 V. The overcharge release
voltage (VCL) is defined by the voltage between VDD and VSS at which VCO goes “H” from “L” when the voltage V1 is
then gradually decreased.
Gradually decreasing the voltage V1, the overdischarge detection voltage (VDL) is defined by the voltage between VDD
and VSS at which VDO goes “L” from “H”. The overdischarge release voltage (VDU) is defined by the voltage between
VDD and VSS at which VDO goes “H” from “L” when the voltage V1 is then gradually increased.
(2) Test Condition 2, Test Circuit 1
(Overcurrent 1 detection voltage, Overcurrent 2 detection voltage, Load short-circuiting detection voltage)
The overcurrent 1 detection voltage (VIOV1) is defined by the voltage between VDD and VSS at which VDO goes “L” from
“H” when the voltage V2 is gradually increased from the normal condition V1 = 3.5 V and V2 = 0 V.
The overcurrent 2 detection voltage (VIOV2) is defined by the voltage between VDD and VSS at which VDO goes “L” from
“H” when the voltage V2 is increased at the speed between 1 ms and 4 ms from the normal condition V1 = 3.5 V and V2
= 0 V.
The load short-circuiting detection voltage (VSHORT) is defined by the voltage between VDD and VSS at which VDO goes
“L” from “H” when the voltage V2 is increased at the speed between 1 μs and 50 μs from the normal condition V1 = 3.5
V and V2 = 0 V.
(3) Test Condition 3, Test Circuit 1
(Charger detection voltage, ( = abnormal charge current detection voltage) )
• Applied only for products with overdischarge hysteresis
Set V1 = 1.8 V and V2 = 0 V under overdischarge condition. Increase V1 gradually, set V1 = (VDU+VDL) / 2 (within
overdischarge hysteresis, overdischarge condition), then decrease V2 from 0 V gradually. The voltage between VM
and VSS at which VDO goes “H” from “L” is the charger detection voltage (VCHA).
• Applied only for products without overdischarge hysteresis
Set V1 = 3.5 V and V2 = 0 V under normal condition. Decrease V2 from 0 V gradually. The voltage between VM and
VSS at which VCO goes “L” from “H” is the abnormal charge current detection voltage. The abnormal charge current
detection voltage has the same value as the charger detection voltage (VCHA).
(4) Test Condition 4, Test Circuit 1
(Normal operation current consumption, Power-down current consumption, Overdischarge current
consumption)
Set V1 = 3.5 V and V2 = 0 V under normal condition. The current IDD flowing through VDD pin is the normal operation
consumption current (IOPE).
•
For products with power-down function
Set V1 = V2 = 1.5 V under overdischarge condition. The current IDD flowing through VDD pin is the power-down
current consumption (IPDN).
•
For products without power-down function
Set V1 = V2 = 1.5 V under overdischarge condition. The current IDD flowing through VDD pin is the overdischarge
current consumption (IOPED).
Seiko Instruments Inc.
15
SII [ SEIKO INSTRUMENTS INC ]
