SAB 82525
SAB 82526
SAF 82525
SAF 82526
HSCX supports target synchronous as well as source synchronous DMA transfer. In source
synchronous DMA transfer mode a DMA cycle is started when an active level occurs an the
DMA request line. This request is controlled by the source (transfer peripheral device →
memory).
First of all the data is read out of the peripheral device. During the second clock cycle it is writ-
ten into the memory according to the target address.
If there is target synchronous DMA transfer the DMA cycle is started when there is an active
level on the DMA request line. The request is controlled by the target (transfer memory →
peripheral).
First of all the data is read from the memory. During the second clock cycle it is written into the
peripheral IC. The DMA request line continues being activated until it is reset by a write cycle
to a peripheral device IC.
T1
T2
T3
T4
T1
T2
T3
T4
CLOCKOUT
DRQ
RD
(FIFO)
WR
(Memory)
ITD02697
tCLRL
t INVCL
t DRHSYS
tDRHSYS
max = T2 + T3 + T4 - t CLRL - t INVCL = 3 x tCLCL - tCLRL - tINVCL
fCLKOUT
tCLCL
tCLRL
tINVCL
tDRHSYS
max
8 MHz
125 ns
80 ns
44 ns
37 ns
31ns
15 ns
15 ns
15 ns
316 ns
188 ns
141.5 ns
12.5 MHz
16 MHz
62.5 ns
Semiconductor Group
44
SIEMENS [ Siemens Semiconductor Group ]
