SAB 82525
SAB 82526
SAF 82525
SAF 82526
T1
T2
T3
T4
T1
T2
T3
T4
CLOCKOUT
DRQTx
DRQ
RD
(Memory)
tCHCSX
CS
(FIFO)
tCVCTV
WR
ITD02700
(FIFO)
tCLCSV
tDRHSYS
tDRHSYS
= T2 + T3 + T4/2 - tCVCTV + tCHCSX
max
fCLKOUT
tCLCL
tCVCTV
tCHCSX
tDRHSYS
max
8 MHz
125 ns
80 ns
56 ns
47 ns
31ns
5 ns
5 ns
5 ns
261ns
158 ns
130 ns
12.5 MHz
16 MHz
62.5 ns
The circuit mentioned above results in a slower data transfer with the HSCX. HSCX usually
performs block transfers. The block length is up to 32 bytes. The DMA request line of the IC
remains active as long as more data are needed. Having transmitted the last byte the DMA
request is being reset. Using the additional circuit the DMA request line will be active at least
shortly before T4. So the next DMA cycle will be started four (instead of two) clock cycles later.
Therefore the maximum transmission rate is reduced from 1.25 Mbyte/s to 1.04 Mbyte/s (clock
rate: 12.5 MHz).
For more information refer to chapter 7.2 (Data Transmission: DMA Mode), chapter 7.3 (Data
Reception: DMA mode), and Appendix C (Application Example HSCX with 80(C)188 using
DMA).
Semiconductor Group
46
SIEMENS [ Siemens Semiconductor Group ]
