LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
2.5 ns OF 50 Ω TRANSMISSION LINE
2.4
2.0
0.8
2.0
0.8
INPUT
0.45
TEST POINTS
OUTPUT
FROM OUTPUT
UNDER TEST
TEST
POINT
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL
(0.45 VTTL) for a Logic '0'. Input timing begins at VIH (2.0 VTTL
)
TOTAL CAPACITANCE = 50 pF
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise
and fall times (10% to 90%) < 10 ns.
28F800SUR-8
28F800SUR-6
Figure 9. Transient Equivalent Testing
Load Circuit (V = 3.3 V)
Figure 7. Transient Input/Output
CC
Reference Waveform (V = 5.0 V)
CC
2.5 ns OF 25 Ω TRANSMISSION LINE
TEST
3.0
INPUT
1.5
1.5 OUTPUT
TEST POINTS
FROM OUTPUT
UNDER TEST
0.0
POINT
NOTE:
AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a
Logic '0'. Input timing begins and output timing ends at 1.5 V.
Input rise and fall times (10% to 90%) < 10 ns.
TOTAL CAPACITANCE = 100 pF
28F800SUR-7
28F800SUR-9
Figure 8. Transient Input/Output
Figure 10. Transient Equivalent Testing
Reference Waveform (V = 3.3 V)
Load Circuit (V = 5.0 V)
CC
CC
2.5 ns OF 83W TRANSMISSION LINE
FROM OUTPUT
UNDER TEST
TEST
POINT
TOTAL CAPACITANCE = 30 pF
28F800SUR-18
Figure 11. High Speed Transient Equivalent
Testing Load Circuit (V = 5.0 V ± 5%)
CC
18
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
