SX1231
ADVANCED COMMUNICATIONS & SENSING
DATASHEET
7
FifoFull
r
0
Set when FIFO is full (i.e. contains 66 bytes), else
cleared.
RegIrqFlags2
(0x28)
6
5
FifoNotEmpty
FifoLevel
r
r
0
0
Set when FIFO contains at least one byte, else cleared
Set when the number of bytes in the FIFO strictly exceeds
FifoThreshold, else cleared.
4
FifoOverrun
rwc
0
Set when FIFO overrun occurs. (except in Sleep mode)
Flag(s) and FIFO are cleared when this bit is set. The
FIFO then becomes immediately available for the next
transmission / reception.
3
2
PacketSent
r
r
0
0
Set in Tx when the complete packet has been sent.
Cleared when exiting Tx.
PayloadReady
Set in Rx when the payload is ready (i.e. last byte
received and CRC, if enabled and CrcAutoClearOff is
cleared, is Ok). Cleared when FIFO is empty.
1
0
CrcOk
r
0
-
Set in Rx when the CRC of the payload is Ok. Cleared
when FIFO is empty.
LowBat
rwc
rw
Set when the battery voltage drops below the Low Battery
threshold. Cleared only when set by the user.
7-0 RssiThreshold
7-0 TimeoutRxStart
0xE4 RSSI trigger level for Rssi interrupt :
- RssiThreshold / 2 [dBm]
RegRssiThresh
(0x29)
*
rw
0x00 Timeout interrupt is generated TimeoutRxStart*16*Tbit
RegRxTimeout1
(0x2A)
after switching to Rx mode if Rssi interrupt doesn’t occur
(i.e. RssiValue > RssiThreshold)
0x00: TimeoutRxStart is disabled
7-0 TimeoutRssiThresh
rw
0x00 Timeout interrupt is generated TimeoutRssiThresh*16*Tbit
RegRxTimeout2
(0x2B)
after Rssi interrupt if PayloadReady interrupt doesn’t
occur.
0x00: TimeoutRssiThresh is disabled
Rev 2 - Nov 2009
Page 68
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