SX1231
DATASHEET
ADVANCED COMMUNICATIONS & SENSING
7-4 ListenResol
rw
1010 Resolution of Listen modes timings (calibrated RC osc):
RegListen1
(0x0D)
*
0101 Æ 64 us
1010 Æ 4.1 ms
1111 Æ 262 ms
Others Æ reserved
3
ListenCriteria
rw
rw
0
Criteria for packet acceptance in Listen mode:
0 Æ signal strength is above RssiThreshold
1 Æ signal strength is above RssiThreshold and
SyncAddress matched
2-1 ListenEnd
01
Action taken after acceptance of a packet in Listen mode:
00 Æ chip stays in Rx mode. Listen mode stops and must
be disabled (see section 4.3).
01 Æ chip stays in Rx mode until PayloadReady or
Timeout interrupt occurs. It then goes to the mode defined
by Mode. Listen mode stops and must be disabled (see
section 4.3).
10 Æ chip stays in Rx mode until PayloadReady or
Timeout interrupt occurs. Listen mode then resumes in
Idle state. FIFO content is lost at next Rx wakeup.
11 Æ Reserved
0
-
r
0
unused
7-0 ListenCoefIdle
rw
0xf5 Duration of the Idle phase in Listen mode.
RegListen2
(0x0E)
tListenIdle = ListenCoefIdle⋅ ListenResol
7-0 ListenCoefRx
rw
r
0x20 Duration of the Rx phase in Listen mode (startup time
included, see section 4.2.3)
RegListen3
(0x0F)
tListenRx = ListenCoefRx⋅ ListenResol
7-0 Version
0x21 Version code of the chip. Bits 7-4 give the full revision
number; bits 3-0 give the metal mask revision number.
RegVersion
(0x10)
Rev 2 - Nov 2009
Page 62
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