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SX1232 参数 Datasheet PDF下载

SX1232图片预览
型号: SX1232
PDF下载: 下载PDF文件 查看货源
内容描述: 高链路预算集成的UHF收发器 [High Link Budget Integrated UHF Transceiver]
分类和应用:
文件页数/大小: 97 页 / 1338 K
品牌: SEMTECH [ SEMTECH CORPORATION ]
 浏览型号SX1232的Datasheet PDF文件第67页浏览型号SX1232的Datasheet PDF文件第68页浏览型号SX1232的Datasheet PDF文件第69页浏览型号SX1232的Datasheet PDF文件第70页浏览型号SX1232的Datasheet PDF文件第72页浏览型号SX1232的Datasheet PDF文件第73页浏览型号SX1232的Datasheet PDF文件第74页浏览型号SX1232的Datasheet PDF文件第75页  
SX1232  
WIRELESS & SENSING  
DATASHEET  
Name  
(Address)  
Default  
value  
Bits  
Mode  
Variable Name  
Description  
RegOokPeak  
(0x14)  
7-6  
5
reserved  
rw  
rw  
0x00 reserved  
BitSyncOn  
0x01 Enables the Bit Synchronizer.  
0 Æ Bit Sync disabled (not possible in Packet mode)  
1 Æ Bit Sync enabled  
4-3  
2-0  
OokThreshType  
rw  
rw  
0x01 Selects the type of threshold in the OOK data slicer:  
00 Æ fixed threshold  
01 Æ peak mode (default)  
10 Æ average mode  
11 Æ reserved  
OokPeakTheshStep  
0x00  
Size of each decrement of the RSSI threshold in the OOK  
demodulator:  
000 Æ 0.5 dB  
010 Æ 1.5 dB  
100 Æ 3.0 dB  
110 Æ 5.0 dB  
001 Æ 1.0 dB  
011 Æ 2.0 dB  
101 Æ 4.0 dB  
111 Æ 6.0 dB  
RegOokFix  
(0x15)  
7-0  
7-5  
OokFixedThreshold  
OokPeakThreshDec  
rw  
rw  
0x0C Fixed threshold for the Data Slicer in OOK mode  
Floor threshold for the Data Slicer in OOK when Peak mode is  
used  
RegOokAvg  
(0x16)  
0x00  
Period of decrement of the RSSI threshold in the OOK  
demodulator:  
000 Æ once per chip  
010 Æ once every 4 chips  
100 Æ twice in each chip  
001 Æ once every 2 chips  
011 Æ once every 8 chips  
101 Æ 4 times in each chip  
110 Æ 8 times in each chip 111 Æ 16 times in each chip  
4
reserved  
rw  
rw  
0x01 reserved  
3-2  
OokAverageOffset  
0x00 Static offset added to the threshold in average mode in order  
to reduce glitching activity (OOK only):  
00 Æ 0.0 dB  
01 Æ 2.0 dB  
10 Æ 4.0 dB  
11 Æ 6.0 dB  
1-0  
7-0  
OokAverageThreshFilt  
reserved  
rw  
rw  
0x02  
Filter coefficients in average mode of the OOK demodulator:  
00 Æ f chip rate / 32.π 01 Æ f chip rate / 8.π  
C
C
10 Æ f chip rate / 4.π  
11 Æf chip rate / 2.π  
C
C
RegRes17  
to  
RegRes19  
0x47 reserved. Keep the Reset values.  
0x32  
0x3E  
RegAfcFei  
(0x1a)  
7-5  
4
unused  
AgcStart  
r
-
unused  
wt  
rw  
-
0x00 Triggers an AGC sequence when set to 1.  
0x00 reserved  
3
reserved  
2
unused  
-
unused  
1
AfcClear  
wc  
rw  
0x00 Clear AFC register set in Rx mode. Always reads 0.  
0
AfcAutoClearOn  
0x00 Only valid if AfcAutoOn is set  
0 Æ AFC register is not cleared at the beginning of the  
automatic AFC phase  
1 Æ AFC register is cleared at the beginning of the automatic  
AFC phase  
Rev 3 - August 2012  
Page 71  
www.semtech.com  
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