SX1232
WIRELESS & SENSING
DATASHEET
3.3. Frequency Synthesis
3.3.1. Reference Oscillator
The crystal oscillator is the main timing reference of the SX1232. It is used as a reference for the frequency synthesizer
and as a clock for the digital processing.
The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. The SX1232
optimizes the startup time and automatically triggers the PLL when the XO signal is stable.
An external clock can be used to replace the crystal oscillator, for instance a tight tolerance TCXO. To do so, TcxoInputOn
in RegTcxo should be set to 1, and the external clock has to be provided on XTA (pin 4). XTB (pin 5) should be left open.
The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an
appropriate value of decoupling capacitor, C .
D
XTA
OP
XTB
NC
TCXO
32 MHz
Vcc
GND
Vcc
CD
Figure 5. TCXO Connection
3.3.2. CLKOUT Output
The reference frequency, or a fraction of it, can be provided on DIO5 (pin 12) by modifying bits ClkOut in RegDioMapping2.
Two typical applications of the CLKOUT output include:
To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be
made available in any operation mode except Sleep mode and is automatically enabled at power on reset.
To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the
initial crystal tolerance.
Note to minimize the current consumption of the SX1232, please ensure that the CLKOUT signal is disabled when not
required.
3.3.3. PLL Architecture
The local oscillator of the SX1232 is derived from a fractional-N PLL that is referenced to the crystal oscillator circuit. Two
PLLs are available for transmit mode operation - either low phase noise or low current consumption to maximize either
transmit power consumption or transmit spectral purity. Both PLLs feature a programmable bandwidth setting where one of
four discrete preset bandwidths may be accessed. For reference the relative performance of both low consumption and low
phase noise PLL, for each programmable bandwidth setting, is shown in the following figure.
Rev 3 - August 2012
Page 19
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