SC4607
POWER MANAGEMENT
Application Information (Cont.)
C1 + C2
R1 C1 C2
ωP1
=
Layout Guidelines:
1
=
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, special at-
tention must be paid to the PCB layouts. The goal of lay-
out optimization is to identify the high di/dt loops and
minimize them. The following guideline should be used to
ensure proper functions of the converters.
ωP2
R8 C9
After the compensation, the converter will have the fol-
lowing loop gain:
s
1+
1
s
s
ωZ2
s
1
ωI
V
1+
1+
1+
1+
I
VM
ωZ1
s
RC C4
1+ s + s2L1C
T(s) = GPWM GCOMP(s) GVD(s) =
L1
R
s
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power compo-
nents first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
ωP1
ωP2
Where:
GPWM = PWM gain
VM = 1.0V, ramp peak to valley voltage of SC4607
The design guidelines for the SC4607 applications are
as following:
3. The Vcc bypass capacitor should be placed next to
the Vcc and GND pins.
1. Set the loop gain crossover corner frequency ω C
for given switching corner frequency ωS = 2πfs,
2. Place an integrator at the origin to increase DC
and low frequency gains.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components.
3. Select ωZ1 and ωZ2 such that they are placed near
ωO to damp the peaking and the loop gain has a
-20dB/dec rate to go across the 0dB line for
obtaining a wide bandwidth.
4. Cancel the zero from C4’s ESR by a compensator
pole ωP1 (ωP1 = ωESR = 1/( RCC4)).
5. Place a high frequency compensator pole ωp2 (ωp2
= πfs) to get the maximum attenuation of the switch-
ing ripple and high frequency noise with the adequate
phase lag at ωC.
5. Minimize the traces between DRVH/DRVL and the
gates of the MOSFETs to reduce their impedance to
drive the MOSFETs.
6. Minimize the loop including input capacitors, top/bot-
tom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
7. ISET and PHASE connections to the top MOSFET for
current sensing must use Kelvin connections.
8. Maximize the trace width of the loop connecting the
inductor, bottom MOSFET and the output capacitors.
The compensated loop gain will be as given in Figure 6:
9. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC4607 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible
T(s)
Loop gain T(s)
ωz1
ωo
ωz2
-20dB/dec
Gvd
0dB
ωc
ωp1
ωp2
Power stage
GVD(s)
ωESR
-40dB/dec
Figure 6. Asymptotic diagrams of power stage and its
loop gain.
2005 Semtech Corp.
13
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SEMTECH [ SEMTECH CORPORATION ]
