SC4215
POWER MANAGEMENT
Applications Information
Enable: Pulling this pin below 0.4V turns the regulator off,
reducing the quiescent current to a fraction of its operat-
ing value. A pull up resistor up to 400kOhms should be
connected from this pin to the VIN pin in application where
supply voltages of Vin < 1.9V is required. For applications
with higher voltages than 1.9V, EN pin could be left open
or connected to VIN.
Introduction
The SC4215 is intended for applications where high cur-
rent capability and very low dropout voltage are required.
It provides a very simple, low cost solution that uses very
little pcb real estate. Additional features include an en-
able pin to allow for a very low power consumption standby
mode, and a fully adjustable output.
Thermal Considerations
Component Selection
The power dissipation in the SC4215 is approximately equal
to the product of the output current and the input to out-
put voltage differential:
Input capacitor: A minimum of 4.7µF ceramic capacitor is
recommended to be placed directly next to the Vin pin.
This allows for the device being some
distance from any bulk capacitance on the rail.
Additionally, bulk capacitance of about ≥ 10µF/A (output
load) may be added closely to the input supply pin of the
SC4215 to ensure that Vin does not sag, improving load
transient response.
PD
≈
VIN − VOUT • IO
( )
The absolute worst-case dissipation is given by:
PD(MAX
=
(
VIN (MAX − VOUT
)
• IO(MAX + VIN (MAX • IQ (MAX
(MIN ) ) ) )
)
)
Output capacitor: A minimum bulk capacitance of
≥ 10µF/A (output load), along with a 0.1µF ceramic de-
coupling capacitor is recommended. Increasing the bulk
capacitance will improve the overall transient response.
The use of multiple lower value ceramic capacitors in par-
allel to achieve the desired bulk capacitance will not cause
stability issues. Although designed for use with ceramic
output capacitors, the SC4215 is extremely tolerant of out-
put capacitor ESR values and thus will also work comfort-
ably with tantalum output capacitors.
For a typical scenario, VIN = 3.3V ± 5%, VOUT = 2.8V and
IO = 1.5A, therefore:
VIN(MAX) = 3.465V, VOUT(MIN) = 2.744V and IQ(MAX) = 1.75mA,
Thus PD(MAX) = 1.09W.
Using this figure, and assuming TA(MAX) = 70°C, we can cal-
culate the maximum thermal impedance allowable to main-
tain TJ ≤ 150°C:
Noise immunity: In very electrically noisy environments, it
is recommended that 0.1µF ceramic capacitors be placed
from IN to GND and OUT to GND as close to the device pins
as possible.
T
− TA(MAX )
PD(MAX )
(
)
=
(
)
150 − 70
1.09
J(MAX )
RTH(J− A)(MAX )
=
= 73.4° C / W
This should be achievable for the SOIC-8EDP package us-
ing pcb copper area to aid in conducting the heat away,
such as one square inch of copper connected to the ex-
posed die pad of the device. Internal ground/power planes
and air flow will also assist in removing heat. For higher
ambient temperatures it may be necessary to use addi-
tional copper area.
Internal voltage selection: By connecting the ADJ pin to
GND, an internal resistor divider will regulate the output
voltage to 2.5V. If the ADJ pin is connected directly to the
VO pin, the output voltage will be regulated to the 0.8V
internal reference.
External voltage selection resistors: the use of 1%
resistors, and designing for a current flow ≥ 10µA is
recommended to ensure a well regulated output
(thus R2 ≤ 50kΩ).
2006 Semtech Corp.
7
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