E0C63466
s
PIN DESCRIPTION
Pin name
V
DD
V
SS
V
D1
V
C1–
V
C5
Pin No.
QFP8-144,QFP17-144
31
25
28
75–79
QFP5-128
64
58
61
101–105
In/Out
–
–
–
–
Function
Power (+) supply pin
Power (–) supply pin
Oscillation/internal logic system regulated voltage output pin
LCD system power supply pin
1/4 bias generated internally, 1/5 bias supplied externally
(selected by mask option)
LCD system power supply testing pin
LCD system boosting/reducing capacitor connecting pin
Crystal or CR oscillation input pin (selected by mask option)
Crystal or CR oscillation output pin (selected by mask option)
Ceramic or CR oscillation input pin
(selected by mask option)
Ceramic or CR oscillation output pin
(selected by mask option)
Input port
Input port
Input port
Input port
I/O port
I/O port (switching to serial I/F input/output is possible by software)
I/O port
I/O port
I/O port (switching to CL signal output is possible by software)
I/O port (switching to FR signal output is possible by software)
Output port
Output port
Output port (switching to TOUT signal output is possible by software)
Output port (switching to FOUT signal output is possible by software)
Output port
Output port
LCD common output pin
(1/8, 1/16, 1/17 duty can be selected by software)
LCD segment output pin
Sound output pin
SVD external voltage input pin
Initial reset input pin
Testing input pin
V
REF
CA–CF
OSC1
OSC2
OSC3
OSC4
K00–K03
K10, K11
K12
K13
P00–P03
P10–P13
P20
P21
P22
P23
R00
R01
R02
R03
R10–R13
R20–R23
COM0, COM1
COM2–COM14
COM15, COM16
SEG0–SEG59
BZ
SVD
RESET
TEST
34
85–80
26
27
29
30
70–67
66,65
64
63
62–59
58–55
54
53
52
51
50
49
48
47
46–43
42–39
23,22
21,20,18–15,86–92
93,94
14–1,143–110,106–95
24
74
32
33
67
111–106
59
60
62
63
99–96
95,94
–
93
92–89
88–85
84
83
82
81
80
79
78
77
76–73
72–69
–
56–51,112–118
–
50–1,128–119
57
100
65
66
O
–
I
O
I
O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
s
ELECTRICAL CHARACTERISTICS
q
Absolute Maximum Ratings
(V
SS
=0V)
Item
Value
Unit
Symbol
Supply voltage
-0.5 to 7.0
V
V
DD
Input voltage (1)
V
I
-0.5 to V
DD
+ 0.3
V
Input voltage (2)
V
IOSC
-0.5 to V
D1
+ 0.3
V
Permissible total output current
∗
1
ΣI
VDD
10
mA
Operating temperature
Topr
-20 to 70
°C
Storage temperature
Tstg
-65 to 150
°C
(lead section)
Soldering temperature / time
Tsol
260°C, 10sec
–
Permissible dissipation
∗
2
P
D
250
mW
∗1
The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pin (or is drawn in).
∗2
In case of plastic package (QFP8-144pin, QFP17-144pin, QFP5-128pin).
5
SEIKO [ SEIKO EPSON CORPORATION ]
