E0C63466
s
BASIC EXTERNAL CONNECTION DIAGRAM
LCD panel 60
×
17
COM0
|
COM16
SEG0
|
SEG59
Input
K00–K03
K10–K13
I/O
X'tal
Output
R00
R01
R02 (TOUT)
R03 (FOUT)
R10–R13
R20–R23
OSC2
OSC3
CR
R
CR1
P00–P03
P10 (SIN)
P11 (SOUT)
P12 (SCLK)
P13 (SRDY)
P20
E0C63466
P21
P22 (CL)
[The potential of the substrate
P23 (FR)
(back of the chip) is V
SS
.]
SVD
CA
CB
CC
CD
CE
CF
TEST
V
DD
V
D1
V
REF
OSC1
C
1
C
2
C
3
C
4
C
9
C
GX
+
C
P
(1.8 V)
2.2 V
|
6.4 V
∗
1
C
GC
C
DC
∗
3
C
RES
∗
2
R
CR2
∗
2
OSC4
RESET
V
C1
V
C2
V
C3
V
C4
V
C5
BZ
V
SS
∗1:
Crystal oscillation
∗2:
CR oscillation
∗3:
Ceramic oscillation
C
5
C
6
Piezo
Coil
X'tal
C
GX
R
CR1
CR
C
GC
C
DC
R
CR2
C
1
–C
8
C
9
C
P
C
RES
Crystal oscillator
Trimmer capacitor
Resistor for OSC1 CR oscillation
Ceramic oscillator
Gate capacitor
Drain capacitor
Resistor for OSC3 CR oscillation
Capacitor
Capacitor
Capacitor
RESET terminal capacitor
32.768 kHz, C
I
(Max.) = 34 kΩ
5–25 pF
600 kΩ (60 kHz)
4 MHz (3.0 V)
30 pF
30 pF
47 kΩ (1.8 MHz)
0.2
µF
0.1
µF
Note: The above table is simply
3.3
µF
an example, and is not
0.1
µF
guaranteed to work.
C
7
C
8
9
SEIKO [ SEIKO EPSON CORPORATION ]
