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E0C63466F 参数 Datasheet PDF下载

E0C63466F图片预览
型号: E0C63466F
PDF下载: 下载PDF文件 查看货源
内容描述: [4-BIT, MROM, 4.1MHz, MICROCONTROLLER, PQFP144, PLASTIC, QFP17-144]
分类和应用: 时钟外围集成电路
文件页数/大小: 11 页 / 102 K
品牌: SEIKO [ SEIKO EPSON CORPORATION ]
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E0C63466
q
SVD Circuit and Current Consumption
(Unless otherwise specified: V
DD
=3.0V, V
SS
=0V, f
OSC1
=32.768kHz, C
G
=25pF, R
CR1
=600kΩ, R
CR2
=47kΩ, Ta=25°C,
V
D1
/V
C1
/V
C2
/V
C4
/V
C5
are internal voltage, C
1
–C
8
=0.2µF)
Item
Min.
Typ.
Max. Unit
Symbol
Condition
SVD voltage
1.85
V
SVD1
SVDS0–3="0" (internal)
1.90
SVDS0–3="1"
2.00
SVDS0–3="2"
2.10
SVDS0–3="3"
2.20
SVDS0–3="4"
2.30
SVDS0–3="5"
2.40
SVDS0–3="6"
Typ.
2.50
Typ.
V
SVDS0–3="7"
×0.93
2.60
×1.07
SVDS0–3="8"
2.70
SVDS0–3="9"
2.80
SVDS0–3="10"
2.90
SVDS0–3="11"
3.00
SVDS0–3="12"
3.10
SVDS0–3="13"
3.20
SVDS0–3="14"
3.30
SVDS0–3="15"
4
SVD voltage (external)
V
SVD2
SVDS0–3="0" (external)
0.95
1.05
1.15
V
100
µS
SVD circuit response time
t
SVD
1
2
µA
Current consumption
I
OP
During HALT (32 kHz crystal oscillation),
LCD power OFF
1
,
2
,
3
6
12
µA
During HALT (32 kHz crystal oscillation),
LCD power ON (V
C1
standard)
1
,
2
,
3
4
8
µA
During HALT (32 kHz crystal oscillation),
LCD power ON (V
C2
standard)
1
,
2
,
3
23
45
µA
During HALT (60 kHz CR oscillation),
LCD power OFF
1
,
3
30
60
µA
During HALT (60 kHz CR oscillation),
LCD power ON (V
C1
standard)
1
,
3
During HALT (60 kHz CR oscillation),
26
50
µA
LCD power ON (V
C2
standard)
1
,
3
10
19
µA
During execution (32 kHz crystal oscillation),
LCD power ON (V
C1
standard)
1
,
2
,
3
45
80
µA
During execution (60 kHz CR oscillation),
LCD power ON (V
C1
standard)
1
,
3
600
800
µA
During execution (2 MHz ceramic oscillation),
LCD power ON (V
C1
standard)
1
During execution (4 MHz ceramic oscillation),
1,200 1,400
µA
LCD power ON (V
C1
standard)
1
During execution (1,800 kHz CR oscillation),
800
1,000
µA
LCD power ON (V
C1
standard)
1
1
7
µA
SVD circuit current (during supply voltage detection)
V
DD
=1.85 to 6.4 V
0.5
3
µA
SVD circuit current (during external voltage detection)
V
DD
=1.85 to 6.4 V
∗1
Without panel load. The SVD circuit is OFF.
∗2
VDC = "0"
∗3
OSCC = "0"
∗4
Please input the voltage, which is within the range between V
SS
and V
DD
, into the SVD terminal.
7