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LC89057W-VF4A-E 参数 Datasheet PDF下载

LC89057W-VF4A-E图片预览
型号: LC89057W-VF4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 数字音频接口收发器 [Digital Audio Interface Transceiver]
分类和应用:
文件页数/大小: 59 页 / 329 K
品牌: SANYO [ SANYO SEMICON DEVICE ]
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LC89057W-VF4A-E  
10.4.6 Processing during error recovery  
When preambles B, M, and W are detected, PLL becomes locked and data demodulation begins.  
RDATA output data is output from the RLRCK edge after RERR turns to "L".  
45ms to 300ms  
RERR  
OK  
Internal lock signal  
RLRCK  
Data  
RDATA  
Output start from RLRCK edge  
immediately after RERR flag is lowered  
Figure 10.12 Data processing when data demodulation starts  
10.5 Channel Status Data Output  
________  
10.5.1 Data delimiter bit 1 output (AUDIO)  
____________  
____________  
AUDIO outputs bit 1 of the channel status that indicates whether the input bi-phase data is PCM audio data. AUDIO is  
immediately output upon detection of RERR even during "H" output period.  
OR-output with IEC61937 or with the DTS-CD/LD detection flag is also possible with AOSEL.  
____________  
Table 10.6 AUDIO Output  
______  
AUDIO  
Output Conditions  
L
PCM audio data (CS bit 1 = "L")  
Non-audio data (CS bit 1 = "H")  
H
10.5.2 Emphasis information output (EMPHA)  
EMPHA outputs shows whether there are 50/15μs emphasis parameters for consumer and broadcast studio.  
EMPHA is immediately output upon detection of RERR even during "H" output.  
Table 10.7 EMPHA Output  
EMPHA  
Output Conditions  
L
No pre-emphasis  
H
50/15μs pre-emphasis  
No.7202-28/59  
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