LC89057W-VF4A-E
10.3.3 Output data switching (SDIN, RDATA)
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RDATA outputs demodulation data when the PLL is locked, and outputs SDIN input data when the PLL is unlocked.
This output is automatically switched according to the PLL locked/unlocked status. For details, see the timing charts
below.
•
•
When SDIN input data is selected, switch to a clock source synchronized to the SDIN data.
With the RDTSTA setting, the SDIN input data is output to RDATA regardless of the locked/unlocked status of the
PLL.
•
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With the RDTMUT setting, the RDATA output data can be also muted forcibly.
Even when the clock source is set to XIN with OCKSEL and RCKSEL, the PLL continues operating as long as the
PLL is not stopped with PLLOPR. At this time, the PLL status is continuously output from RERR unless error output
is forcibly set with RESTA. Moreover, the processed information can be read with the microcontroller interface
regardless of the PLL status.
PLL status
CKST
UNLOCK
LOCK
RERR
RDATA
SDIN data
LOCK
Muted
Demodulation data
(a): Lock-in stage
PLL status
CKST
UNLOCK
RERR
RDATA
Demodulation data
Muted
SDIN data
(b): Unlock stage
Figure 10.9 Timing Chart of RDATA Output Data Switching
No.7202-24/59
SANYO [ SANYO SEMICON DEVICE ]
