LC786960E
Communication Timing specification between Host controller
SIFCE
(Input)
1/fCLK
tCSU
tCKH
tCKL
tCHD
SIFCK
(Input)
tCE
tCWSU tCWHD
SIFDI
(Input)
tCRAS
tCDOF
SIFDO
(Output)
BUSYB
(Output)
tCDOH
tCDON
tCBST
Parameter
SIFCK clock frequency
Symbol
fCLK
Pin names
min
typ
max
unit
3.3
SIFCK
SIFCK
SIFCK
MHz
0.725
150
SIFCK clock "H" level width
SIFCK clock "L" level width
Transfer start enable time
Setup time for transfer start
Hold time for transfer end
Setup time for SIFDI
tCKH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
690
150
690
0
tCKL
tCE
BUSYB, SIFCE
SIFCE, SIFCK
SIFCE, SIFCK
SIFDI, SIFCK
SIFDI, SIFCK
SIFDO, SIFCK
SIFDO, SIFCK
SIFDO, SIFCE
SIFDO, SIFCE
BUSYB
0
100
200
100
200
75
tCSU
tCHD
tCWSU
tCWHD
tCDOH
tCRAS
tCDON
tCDOF
tCBST
75
75
Hold time for SIFDI
200
100
350
100
350
100
100
150
150
150
350
Output delay time for SIFDO “H”
Output delay time for SIFDO
Turn on time for SIFDO *1
Turn off time for SIFDO *1
BUSYB "L" level output delay time
Internal CPU operating speed mode Upper step : Normal speed
Lower step : Low speed
*1: The tCDON and tCDOF specifications are for when the SIFDO pin is set to the 3-State mode.
No.A2080-14/24
SANYO [ SANYO SEMICON DEVICE ]
