LC786960E
Host interface
The data transmission between this LSI and Host controller is performed with SPI type synchronous SIO protocol.
The transmission procedure is as follows.
Refer to the internal software specification of this LSI about M5 to M0 code in Mode code transmission.
When the input data of M5 to M0 coincide to the data in the internal register, the SIFDO pin becomes to “Low”
level (Ack) then the transmission is enabled.
When not coincide, the SIFDO pin keeps “High” level (Nack) then the transmission is not enabled.
The seventh data in Mode code transmission shows whether the following procedure is the Command transmission
or the Data reception. When the seventh data is “Low”, the following procedure is Command transmission. When
the seventh data is “High”, the following procedure is Data reception.
Attention because the specifications of transmission timings are different depending on the internal CPU’s operating
speed modes (Low speed or Normal speed). Refer to the table in next page.
Communication Interface format between Host controller
SIFCE
SIFCK
MODE
Command
MODE
(Send) Com1mand Com2mand
N
(Receive)
SIFDI
Data
1
Data
2
Data
N
SIFDO
BUSYB
Ack
Ack
Transmission/Reception format between Host controller
(1) Host: Command Transmission
SIFCE
1
2
3
4
5
6
7
8
1
2
3
6
7
8
SIFCK
SIFDI
M5 M4 M3 M2 M1 M0 WR
D7 D6 D5
D2 D1 D0
Mode Code
byte
1st-data
byte
Last-data
byte
Nack
Ack
SIFDO
BUSYB
(2) Host: Data Reception
SIFCE
1
2
3
4
5
6
7
8
1
2
3
6
7
8
SIFCK
SIFDI
M5 M4 M3 M2 M1 M0 RD
Mode Code
byte
Nack
SIFDO
BUSYB
Ack D7 D6 D5
D2 D1 D0
1st-data
byte
Last-data
byte
No.A2080-13/24
SANYO [ SANYO SEMICON DEVICE ]
