LC75852E, 75852W
1/2 Duty - 1/2 Bias LCD Drive Scheme
COM1
COM2
S1 to S45 outputs for segments on
COM1 side being lit
S1 to S45 outputs for segments on
COM2 side being lit
S1 to S45 outputs for segments on
COM1,COM2 sides being lit
S1 to S45 outputs for segments on
COM1,COM2 sides not being lit
RES and the Display Controller
Since the LSI internal data (D1 to D90 and the control data) is undefined when power is first applied, the output pins
S1/P1 to S4/P4, S5 to S43, COM1, COM2, KS1/S44 and KS2/S45 should be held low by setting the RES pin low at the
same time as power is applied. Then, meaningless displays at power on can be prevented by transferring data from the
controller and setting RES high when that transfer has completed.
Figure 2
No. 4828-11/16
SANYO [ SANYO SEMICON DEVICE ]
