LA6560
Block Diagram
Signal system GND
FWD
REV
1
2
3
4
5
6
7
8
9
36 S-GND
35 VCONT
34 MUTE
Thermal shutdown
(LOAD output voltage setting)
BTL-AMP Output
V
2
MUTE
CC
ON/OFF
VLO-
33
32
31
V
V
V
4
IN
IN
IN
22kΩ
11kΩ
VLO+
4-
4+
V
4+
O
V
4-
30 VREF-IN
O
V
3+
29
V
1(VREF)-SW
IN
V
1/VREF-SW
IN
O
V
3-
28 VREF-OUT(CH1)
O
Power system GND
Power system GND
FR FR
FR FR
5VREG (Extemal PNP)
V
2+ 10
27 REG-OUT
26 REG-IN
O
V
2- 11
O
22kΩ
V
1+ 12
25
24
23
22
21
20
19
V
V
V
V
V
V
V
3+
3-
O
IN
IN
IN
IN
IN
IN
IN
11kΩ
V
1- 13
O
V
1
1
14
15
3
CC
22kΩ
11kΩ
22kΩ
V
2+
2-
IN
11kΩ
V
1-A 16
IN
[L] [H]
AMP-A
AMP-B
V
1 (VREF)-SW
IN
[L]:Internal VREF (2.5V fixed)
[H]:Internal VREF
V
1+A 17
IN
2
V
1 (VREF)-SW
[L]:AMP-A
[H]:AMP-B
IN
V
1-B 18
IN
1+B
No.A0599-4/9
SANYO [ SANYO SEMICON DEVICE ]
