I/O PORTS
S3C4510B
31 30 29 28 27 26 25
23 22
20 19
15 14
10 9
5
4
3
2
1
0
T T
O O
E E
N N
X
I
R
Q
3
X
I
R
Q
2
X
I
R
Q
1
X
I
R
Q
1
D
A
K
1
D
A
K
0
D
R
Q
1
D
R
Q
0
1
0
[4:0] Control external interrupt request 0 input for port 8 (xIRQ0)
[4] Port 8 for xINTREQ0
0 = Disable
1 = Enable
[3] 0 = Active Low
1 = Active High
[2] 0 = Filtering off
1 = Filtering on
[1:0] 00 = Level detection
01 = Rising edge detection
10 = Falling edge detection
11 = Both edge detection
[9:5] Control external interrupt request 1 input for port 9 (xIRQ1)
(See control external interrupt request 1.)
[14:10] Control external interrupt request 2 input for port 10 (xIRQ2)
(See control external interrupt request 2.)
[19:15] Control external interrupt request 3 input for port 11 (xIRQ3)
(See control external interrupt request 3.)
[22:20] Control external DMA request 0 input for port 12 (DRQ0)
[22] Port 12 for nXDREQ0
0 = Disable
1 = Enable
[21] 0 = Filtering off
1 = Filtering on
[20] 0 = Active Low
1 = Active High
[25:23] Control external DMA request 1 input for port 13 (DRQ1)
[25] Port 13 for nXDREQ1
0 = Disable
1 = Enable
[24] 0 = Filtering off
[23] 0 = Active Low
1 = Filtering on
1 = Active High
[27:26] Control external DMA acknowledge 0 output for port 14 (DAK0)
[27] Port 14 for nXDACK0
0 = Disable
1 = Enable
[26] 0 = Active Low
1 = Active High
[29:28] Control external DMA acknowledge 1 output for port 15 (DAK1)
[29] Port 15 for nXDACK1
0 = Disable
1 = Enable
[28] 0 = Active Low
1 = Active High
[30] Control timeout 0 for port 16 (TOEN0)
0 = Disable
1 = Enable
[31] Control timeout 1 for port 17 (TOEN1)
0 = Disable
1 = Enable
Figure 12-3. I/O Port Control Register (IOPCON)
12-4
SAMSUNG [ SAMSUNG ]
