S3C4510B
HDLC CONTROLLERS
Address (A) Field
The eight bits that follow the opening flag are called address (A) field. The address field are expendable. To
extend this address byte, simply user-defined address write to the station address register. To check address byte
against the incoming data, have to be used the MASK register. If match occurred, the frame's data including
address and CRC(16-bit) into the HRXFIFO and then moved to system memory. If it is not matched, simply
discarded. S3C4510B allows up to 32-bits address. For instance, SDLC and LAPB use an 8-bit address. LAPD
further divides its 16-bit address into different fields to specify various access points one piece of equipment.
Some HDLC-type protocol allows for extended addressing beyond 16-bit.
Control (C) Field
The eight bits that follow the address field are called the control (link control, C) field. The S3C4510B HDLC
module treats the control field in the same way as the information field. That is, it passes the eight bits to the
CPU or memory during reception. The CPU is responsible for how the control field is handled and what happens
to it.
Information (I) Field
The information (I) field follows the control (C) field and precedes the frame check sequence (FCS) field. The
information field contains the data to be transferred. Not every frame, however, must actually contain information
data. The word length of the I-field is eight bits in the S3C4510B HDLC module. And Its total length can be
extended by 8 bits until terminated by the FCS field and the closing flag.
Frame Check Sequence (FCS) Field
The 16 bits that precede the closing flag comprise the frame check sequence (FCS) field. The FCS field contains
the cyclic redundancy check character, CRCC. The polynomial x16 + x12 + x5 + 1 is used both for the
transmitter and the receiver. Both the transmitter and the receiver polynomial registers are all initialized to 1 prior
to calculating of the FCS. The transmitter calculates the frame check sequence of all address bits, control bits,
and information fields. It then transmits the complement of the resulting remainder as the FCS value.
The receiver performs a similar calculation for all address, control, and information bits, as well as for all the FCS
fields received. It then compares the result to F0B8H. When a match occurs, the frame valid (RxFV) status bit is
set to '1'. When the result does not match, the receiver sets the CRC error bit (RxCRCE) to '1'. The transmitter
and the receiver automatically perform these FCS generation, transmission and checking functions. The
S3C4510B HDLC module also supports NO CRC operation mode. In NO CRC mode, transmitter does not
append FCS to the end of data and the receiver also does not check FCS. In this mode, the data preceding the
closing flag is transferred to the HRXFIFO. In CRC mode, the FCS field is transferred to the HRXFIFO.
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SAMSUNG [ SAMSUNG ]
