2
I C BUS CONTROLLER
S3C4510B
Shift Buffer Register (IICBUF)
The shift buffer register for the I2C-bus described in Table 6-4.
Table 6-3. IICBUF Register
R/W Description
R/W Shift buffer register
Register
Offset Address
Rest Value
Undefined
IICBUF
0xf004
Table 6-4. IICBUF Register Description
Description
Bit Number
Bit Name
[7:0]
Data
This data field acts as serial shift register and read buffer for
interfacing to the I2C-bus. All read and write operations to/from the
I2C-bus are done via this register. The IICBUF register is a
combination of a shift register and a data buffer. 8-bit parallel data is
always written to the shift register, and read form the data buffer. I2C-
bus data is always shifted in or out of the shift register.
[31:8]
Reserved
Not applicable.
Prescaler Register (IICPS)
The prescaler register for the I2C-bus is described in Table 6-6.
Table 6-5. IICPS Register
R/W Description
R/W Prescaler register
Register
Offset Address
Rest Value
IICPS
0xf008
0x00000000
Table 6-6. IICPS Register Description
Description
Bit Number
Bit Name
This prescaler value is used to generate the serial I2C-bus clock. The
system clock is divided by (16 x (prescaler value + 1) + 3) to make the
serial I2C clock. If the prescaler value is zero, the system clock is when
divided by 19 to make the serial I2C clock.
[15:0]
Prescaler value
[31:16]
Reserved
Not applicable.
6-10
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