PRODUCT OVERVIEW
S3C4510B
FEATURES
Architecture
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Data alignment logic
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Integrated system for embedded ethernet
applications
Endian translation
100/10-Mbit per second operation
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Fully 16/32-bit RISC architecture
Full compliance with IEEE standard 802.3
MII and 7-wire 10-Mbps interface
Station management signaling
On-chip CAM (up to 21 destination addresses)
Full-duplex mode with PAUSE feature
Long/short packet modes
Little/Big-Endian mode supported basically, the
internal architecture is big-endian.
So, the little-endian mode only support for
external memory.
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Efficient and powerful ARM7TDMI core
Cost-effective JTAG-based debug solution
Boundary scan
PAD generation
System Manager
HDLCs
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8/16/32-bit external bus support for
ROM/SRAM, flash memory, DRAM, and
external I/O
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HDLC protocol features:
— Flag detection and synchronization
— Zero insertion and deletion
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One external bus master with bus request/
acknowledge pins
— Idle detection and transmission
— FCS generation and detection (16-bit)
— Abort detection and transmission
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Support for EDO/normal or SDRAM
Programmable access cycle (0-7 wait cycles)
Four-word depth write buffer
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Address search mode (expandable to 4 bytes)
Selectable CRC or No CRC mode
Automatic CRC generator preset
Digital PLL block for clock recovery
Baud rate generator
Cost-effective memory-to-peripheral DMA
interface
Unified Instruction/Data Cache
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Two-way, set-associative, unified 8K-byte cache
Support for LRU (least recently used) protocol
Cache is configurable as an internal SRAM
NRZ/NRZI/FM/Manchester data formats for
Tx/Rx
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Loop-back and auto-echo modes
Tx/Rx FIFOs have 8-word (8 ´ 32-bit) depth
Selectable 1-word or 4-word data transfer mode
Data alignment logic
I2C Serial Interface
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Master mode operation only
Baud rate generator for serial clock generation
Endian translation
Programmable interrupts
Ethernet Controller
Modem interface
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DMA engine with burst mode
Up to 10 Mbps operation
DMA Tx/Rx buffers (256 bytes Tx, 256 bytes
Rx)
HDLC frame length based on octets
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MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes
Rx)
2-channel DMA buffer descriptor for Tx/Rx on
each HDLC
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SAMSUNG [ SAMSUNG ]
