S3C4510B
INSTRUCTION SET
FORMAT 1: MOVE SHIFTED REGISTER
11
10
3
2
15
14
13
12
6
5
0
Offset5
Rs
Rd
0
0
0
Op
[2:0] Destination Register
[5:3] Source Register
[10:6] Immediate Vale
[12:11] Opcode
0 = LSL
1 = LSR
2 = ASR
Figure 3-30. Format 1
OPERATION
These instructions move a shifted value between Lo registers. The THUMB assembler syntax is shown in
Table 3-8.
NOTE
All instructions in this group set the CPSR condition codes.
Table 3-8. Summary of Format 1 Instructions
OP
THUMB Assembler
ARM Equivalent
Action
00
LSL Rd, Rs, #Offset5
MOVS Rd, Rs, LSL #Offset5
Shift Rs left by a 5-bit immediate value and
store the result in Rd.
01
10
LSR Rd, Rs, #Offset5
ASR Rd, Rs, #Offset5
MOVS Rd, Rs, LSR #Offset5 Perform logical shift right on Rs by a 5-bit
immediate value and store the result in Rd.
MOVS Rd, Rs, ASR #Offset5 Perform arithmetic shift right on Rs by a 5-bit
immediate value and store the result in Rd.
INSTRUCTION CYCLE TIMES
All instructions in this format have an equivalent ARM instruction as shown in Table 3-8. The instruction cycle
times for the THUMB instruction are identical to that of the equivalent ARM instruction.
Examples
LSR
R2, R5, #27
; Logical shift right the contents
; of R5 by 27 and store the result in R2.
; Set condition codes on the result.
3-67
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